The present invention is directed, in general, to a semiconductor device and a method of manufacturing the device. More specifically, the semiconductor device includes an alignment mark with a depth that is substantially equal to a depth of an isolation trench. Further, the alignment mark includes a protective etch stop that is deposited within the alignment mark.
During semiconductor manufacturing processes, layers of various materials are deposited or grown on a wafer. Chemical mechanical polishing (CMP) is the standard technique to planarize oxide in shallow trench isolation (STI) structures. As a result of the CMP step, the wafer surface is very planar, and the only topography remaining is the height of the step created between active areas and the oxide trench. After CMP, the trench oxide can be about 80 nm above the silicon level. However, due to a hydrogen fluoride de-glaze for nitride strip and other oxide removal operations, the step can be reduced to about 10 nm to 30 nm, which creates a topography that can be difficult for a photolithographic tool to detect.
Following STI, gate oxide is grown and the transistor gate stack is deposited. Usually, this stack has an upper metallic layer, such as tungsten silicide (WSi), to reduce total resistivity. The pattern of each layer must be precisely aligned to the patterns of the previous layer to ensure that the device operates properly.
To achieve proper alignment, alignment marks are formed on the wafer and are used by the steppers, so that in each photolithographic step, the mask will be properly aligned according to the marks in the previous layers. Typically the stepper detects the alignment marks through various transparent layers. However, the use of the reflective WSi interferes with the photolithographic process by reflecting interfering light patterns such that the photoresist is not properly exposed.
In such instances, it is difficult to detect the alignment marks through the optically reflective material. In situations where a reflective material overlays the alignment marks, the semiconductor manufacturing industry relies on relief topography at the edge of the alignment feature for accurate alignment. In many situations, however, this relief is too small because of previous processing steps, and alignment not only becomes very difficult, but impossible in extreme cases. Thus, several approaches have been developed to address this problem.
One approach is to use a thicker nitride layer to enhance the height of the step between the trench oxide and the active area. This consists of increasing the nitride layer from the traditional thickness of about 160 nm to a thickness of about 180 nm. However, a problem with the 20 nm increase in thickness is that it is unpredictable whether it will or will not alleviate the problem in a particular instance. Moreover, increasing the nitride thickness typically adds unwanted stresses and deposition complications.
Another approach is to use an extra photo step to etch holes in the trench oxide that form large topography alignment features. The large topography alignment features provide the step height needed, but the large topography alignment features also add an extra photolithographic level, which increases cost and cycle times.
Accordingly, what is needed in the art is an alignment feature for use in semiconductor devices having optically reflective materials located therein, and that does not experience the problems associated with the prior art alignment features.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device and a method of its manufacture. The method of manufacturing the semiconductor device includes forming an isolation trench in a substrate, forming an alignment mark in the substrate and forming an etch stop layer in the alignment mark. As discussed below, the alignment mark provided by the present invention can easily be incorporated into a conventional operative integrated circuit.
In another aspect, the present invention provides a semiconductor device. In one advantageous embodiment, the semiconductor device includes a transistor isolation structure formed in a semiconductor substrate and an alignment mark formed in the semiconductor substrate wherein the alignment mark is substantially free of a nitride layer and has a gate material deposited therein. The transistor isolation structure has a depth and the alignment mark preferably has a depth substantially equal to the depth of the transistor isolation structure, which are set forth in the above-discussed method embodiments. In another aspect, the gate material comprises polysilicon and further includes an oxide layer located under the gate material and a reflective coating located over the gate material. Other embodiments of the semiconductor device include embodiments provided by the above-discussed method embodiments.
Thus, in one aspect, the present invention provides robust alignment features for non-transparent gate layers that can be easily detected by a photolithographic tool. These unique alignment marks not only eliminate the need for a dedicated alignment mark mask, but they also substantially reduce the small step problems currently caused by chemical mechanical polishing processes commonly used during the manufacturing process.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.